Rapid advances of very large scale integrated circuit (VLSI) technologies have made design of integrated circuits increasingly complex and time consuming. Computer-Aided Design (CAD) has become a necessity to speed up and improve the quality of VLSI design. Of all the phases in designing application specific VLSI circuits, physical layout takes up a major portion of the turn-around time.
In creating a physical layout of an application specific VLSI circuit, a computer layout is first generated. Generally, the computer layout is created by arranging a number of individual blocks or "logic cells" according to predetermined schematics. The functionality and design of individual logic cells may be predetermined and stored on a computer system as a standardized design. Such design techniques can save considerable time, as it is no longer necessary for an integrated circuit designer to custom design each individual gate and transistor in an integrated circuit. Rather, the circuit designer breaks down a new circuit design into a number of known (or new) cell designs and then combines these cells appropriately to generate a circuit design which performs a desired function. Each of the logic cells contains a number of terminals for implementing into the integrated circuit. These logic cells are commercially available.
To "tape-out" such a circuit layout, commercial "placeand-route" CAD tools, such as Cell3.TM. from Cadence Design Systems, Inc., of San Jose, Calif., can be utilized. More particularly, place-and-route CAD programs are used 1) to arrange logic cells and other elements to optimize their interconnections and the overall surface area and 2) to define the routing region and to select channels to connect the logic cells and elements. To perform the tasks mentioned above, a place-and-route CAD tool requires as input a predetermined number (including reserves) of predefined logic cell types (e.g., AND-gate, OR-gate, flip-flop, etc.). Information related to the logic cells along with the required terminal connections are provided to the place-and-route CAD tool in a data file called "netlist". In response, the place-and-route CAD tool outputs a circuit layout.
Using the computer layout generated as a blueprint, a number of base, contact, and metal layers defining the elements and interconnections of the VLSI circuit are created in silicon through a combination of semiconductor processes namely depositing, masking, and etching. When combined, these layers form the VLSI circuit. Depending on the complexity of the application specific VLSI circuit, each circuit may involve multiple base layers, multiple contact, and multiple metal layers. This process is widely known as tape-out.
Following tape-out, for various reasons including design changes, modifications are subsequently required to delete as well as add logic elements and interconnections from the VLSI circuit. When this occurs, an engineering change order (ECO) is generated to document the desired changes. Next, the circuit layout generated earlier is modified using the commercial place-and-route CAD tool to incorporate the desired changes. Under the prior art, extra logic cells of different types are included in the original computer layout as reserves in case new elements are needed. However, due to limitations inherent in the software environment (e.g., capability to handle a limited number of variables), the place-and-route CAD tool requires that these extra logic cells be of predefined types and numbers. Because the types of the logic cells are predefined as AND gates, OR gates, flip-flops, etch, modifications are limited to changing the logic cells connectivity. Such inflexibility may cause disastrous consequences. For example, in adding logic elements as required under an ECO, a logic cell of a certain type may not be available for implementing a desired function. As a result, either the desired function must be deleted or the process of generating a computer layout with the desired logic cells must be restarted. As such, neither one of these options are desirable.
Even if the right type logic cells are available for adding, the layout engineer must still make the proper connections. Because the locations of the logic cells are fixed, it is sometimes not possible to provide the desired connections given existing obstacles and various space constraints in the layout. In addition, it is a painful and time consuming task to identify the extra logic cells and provide the proper wiring to properly connect the added cells. Because of the increasing complexity of VLSI circuits, the layout engineer must work with as many as four different layout layers at a time. Given the complexity of the task, under the prior art, the turn-around time to incorporate the desired ECO changes is generally high. Hence, it is desirable to preserve as much of the information generated from the original layout as possible as well as to automate the ECO process to allow ECO changes to be made faster and more efficiently.
In automating the ECO process, net connectivity patterns for configuring logic cells to implement logic functions such as ANDing, ORing, etc. are gathered and stored as a standard cell library. Using the net connectivity patterns in a cell library, a place-and-route CAD tool can automatically configure standard cells on a VLSI circuit layout to perform the desired functions. In so doing, VLSI circuits having the intended logic functions can be fabricated in a short time because the logic cell configuration is made automatically by computers instead of manually by layout engineers.
For application specific integrated circuits (ASIC), there are two major types of logic cells: standard logic cells and gate array cells. For standard logic cells, each logic function is implemented essentially as a custom designed circuit which can be placed anywhere in a circuit layout and then wired to other functions, circuits, or cells. In addition to having optimized performances, the sizes of the devices or transistors in standard logic cells are minimized to save space. As such, once configured, modifications of standard cells can be made by making new mask for every step in the fabrication process starting from the silicon wafer.
Unlike standard cells, gate array cells can be configured to implement the desired functionality by making the required interconnections in the metal layers of the integrated circuits. This is allowed because for gate array cells, any logic function is implemented with the same set of devices or transistors. Accordingly, both initial designs and later modifications of integrated circuits can be made faster and less expensive using gate array cells than using standard cells albeit at great costs in performance and density.
Due to the fundamental difference between standard cells and gate array cells, net connectivity patterns in a standard cell library are not generally applicable to gate array cells. Similarly, net connectivity patterns in a gate array cell library are not generally applicable to standard cells. For various reasons, commercial place-and-route CAD tools, however, generally require that the net connectivity patterns in a gate array cell library be designed for standard logic cells. As such, a VLSI circuit initially designed using standard logic cells and having spare gate array cells for ECO modifications cannot use the standard cell library to automatically configure the spare gate array cells.
Thus, a need exists for a method and system to allow using the net connectivity patterns in a standard cell library to automatically configure gate array cells.